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Digital pulse processing (DPP) systems are known to have better performance than analog ones. DPP can synthesize almost any pulse response shape without the associated signal degradation which happens in a complex analog path. High-speed transient recorders with auto-trigger functionality are used to digitize and store the detailed shape of pulses. Algorithms for Pulse Height Analysis (PHA) and Pulse Shape Discrimination (PSD) are then applied to the digitized pulses on (re-)programmable devices such as FPGAs, DSPs and GPP for data reduction and real-time monitoring.



  • ATCA board with eight acquisition channels per module;
  • Data transfer rate of up to 800 Mbyte/s over x4 PCI Express to the host processor.
  • Choice of 250 MSPS @ 13-bit, 400 MSPS @ 14-bit, 500 MSPS @ 12-bit resolution;
  • Channels can be paired for sampling rates of, respectively, 500, 800, 1000 MSPS with reduced ENOB (~10-bit);
  • Maximum pulse rate of 5 Mpulse/s;
  • 11 bit of ENOB for energies at 4 MeV and up to 20 MeV;
  • 2 Gbytes of raw data memory distributed in two blocks of four channels (~256 Mbytes/ch);
  • Digitally programmable pulse level detection with pre- and pos-trigger configurable number of samples;
  • Hardware coded voltage offset to configure for maximum signal amplitude on the analogue input (-5V to +5V @ 50 ohms);
  • An internall/external start trigger will be present in the module front-panel;
  • Externally/internally clocked/triggered programmable time mark (1 ms nominal) to trigger the storage of the pulse counting value. Between two marks the acquired pulse vector will be used to calculate statistics for that period;
  • The digitizer’s local timing unit for tagging the pulses time will have a resolution up to 1.25 ns and at least one day of time span;
  • Detection of pulse pile-up events.

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